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The 6610 Video Generation Module (VGM) is a VMEbus compatible 9U board designed to output LPRF, HPRF and IFF video and video trigger signals, and also various support signals, used to drive the AWG-9 Radar Detailed Data Display (DDD).


Key Features:

• VMEbus 32-bit Slave access read/write to Video Interface board
• Output trigger rate of 125 HZ generated on board - no need for operating system to stimulate trigger
• LPRF and IFF output settings of 5mi., 10mi., 20mi., 50mi., 100mi. and 200mi. range scales
• LPRF video output capable of delivering an analog signal representing 256 samples or range bins at the various range settings
• IFF video output capable of sending a digital signal representing 256 samples at the various range settings; in 'Expanded Sweep' mode, the IFF video output is delayed and placed in the 20 mile range scale automatically
• HPRF video output capable of sending a digital signal representing 256 samples at a 4.0 uS rate each
• All triggers are generated automatically
• Two banks of memory providing simultaneous write from Silicon Graphics and read to video output
• Read/Write Control Register used to set mode, range and gain of video output
• Read only Status register used to check full and empty flags from the memory and indicate to host which memory bank is currently in use
• Test feature allows user to read memory back to Silicon Graphics
• This Product was designed, built, and in use for the Hughes F-14 AWG-9 Radar Display

Functional Description:

The VGM is a memory-mapped 9u multilayer slave board, communicating to the host processor using the 'Extended Non-Privileged Data Access' mode. The board has a user defined base address that is set using a 8-position DIP switch. The base address must be used for the software to address all functions.

A reset sent to the board initializes all functions, and a read of the status register verifies that the on-board FIFOs are empty. Instructions are then downloaded to the control registers, indicating the mode, trigger mask, range scale (if necessary), and video output gain information. Next, 64 longwords of data, representing 256 bytes of the video data, are sent to either LPRF or HPRF FIFO Bank #0; 32 bits of data are written to the data register, and the status register is read to verify that the FIFO is full. Test reads of the FIFOs may occur to insure data integrity.

At this time, the host sends the 'Start FIFO Bank #0' instruction to start reading Bank #0 FIFO data. This instruction causes data to be read out of the FIFO at a rate determined by the mode and range scale in 'LPRF' or 'IFF' mode.

When 'LPRF' mode is selected, the LPRF video data is sent to a Digital-to-Analog Converter (DAC) and sent out to the display along with a trigger pulse. The gain of the output video signal may be adjusted by the host, as necessary.

When 'IFF' mode is selected, the IFF video, Range gate pulse and 'IFF Delay' trigger are sent out of the board to the display.

When 'IFF Expanded Sweep' mode is selected, the IFF video, Range gate pulse, 'IFF Delay' trigger and 'In 20 Mile Sweep' trigger are sent out of the board to the display.

When 'HPRF' mode is selected, the Threshhold video, Acquisition Display gate and the Threshhold video trigger are sent out of the board.

All digital signals leaving the board use differential line drivers.

The data register is responsible for outputting the Antenna Azimuth and Elevation positions and JAM Intensity info into DAC's, which are then output as analog signals from the board.

Also, the data register outputs 'Jet Display,' 'Radar Scan Left' and 'Gain Time Control' digital signals using differential line drivers.

The host downloads the next 256 bytes of data to the corresponding FIFO Bank #1 and the next 32 bits of data to the data register, and then checks the status register for FIFO full.

The VGM will continue to re-transmit the data out on Bank #0 until the host tells it otherwise. To switch banks, the host reads the status register to determine which bank is currently in use (Bank #0 in this case) and will send an instruction to the video board to 'Start FIFO Bank #1.' Bank #1 will be read only after Bank #0 is empty and on the next 8mSec (125HZ) rate. New data may now be downloaded to Bank #0 and the process is repeated for FIFO Bank #1.


Physical Description:

The VGM is implemented on a triple height d form factor printed circuit board. The board interfaces with the Silicon Graphics VMEbus backplane through two DIN Type "C" connectors that conform with DIN requirement 41612. On the front edge of the board, two 26-pin right angle ribbon M-type connectors are used for all of the digital and analog signals.


Specifications: